Timing analyzer for embedded testing

Abstract

A timing analyzer for embedded testing of printed circuit boards, integrated circuits or multi-chip modules is in the form of an integrated circuit that may be included as part of the printed circuit board, integrated circuit or multi-chip module being tested. Each channel of a data path to be tested has a timing analyzer circuit that may be coupled into the path when enabled for testing. The timing analyzer circuit has instruction memories that are loaded with time event commands via a suitable program bus, such as a boundary scan interface. Each event command has a clock portion, an interpolation portion and a drive output portion. A counter counts down the clock portion using a system clock from the board/circuit/module to produce a terminate pulse. The terminate pulse is delayed by an increment less than one period of the system clock by a delay interpolator, the amount of delay being determined by the interpolation portion, to generate a trigger signal. The trigger signal clocks a capture register to acquire the logic level at a selected one of the pins, and optionally causes a selected output to be driven according to the drive output portion. A shared delay calibration circuit uses a charge-pumped phase locked loop to generate a precision supply voltage for the delay elements in the delay interpolator, the delay for each delay element being a function of the applied supply voltage.