The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 1995
Filed:
Sep. 22, 1993
Meeling Roberts, Fremont, CA (US);
Ronald J Mayer, Folsom, CA (US);
Waleed S Almulla, Folsom, CA (US);
Bradley G Heaney, Mountain View, CA (US);
Gloria Leong, San Mateo, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus having a 3.3 volt power supply and a 5 volt power supply, wherein digital signals are processed on a 3.3 volt basis which are translated to a 5 volt basis by a voltage translation circuit before being output. The voltage translator is comprised of an inverter for inverting an input signal. The inverter is powered by the 3.3 volt power supply. A p-channel transistor having its source coupled to the 5 volt power supply and its gate driven by the output of the inverter is implemented. When the inverter generates a low logic, the p-channel transistor is turned on and outputs 5 volts. An n-channel transistor having its source coupled to ground and its gate driven by the output of the inverter is also implemented. When the output of the inverter is 3.3 volts, the n-channel transistor is turned on, which pulls the output to ground. Therefore, when the input signal is at 3.3 volts, a 5 volt signal is output from the voltage translation circuit. When the input signal is at 0 volts, the output signal is, likewise, at 0 volts.