The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 1995

Filed:

Dec. 15, 1992
Applicant:
Inventors:

Masaaki Niwa, Hirakata, JP;

Masaharu Udagawa, Tokyo, JP;

Yoshihiko Hirai, Shiginonishi, JP;

Juurou Yasui, Toyonaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437132 ; 437238 ; 437239 ; 437919 ; 437939 ; 148D / ; 148D / ; 117 95 ; 117106 ; 117935 ;
Abstract

A method is disclosed of forming semiconductor hetero interfaces that will contribute to the performance improvement of devices having semiconductor hetero interfaces such as MOS transistors, quantum devices, capacitors and the like. The method comprises the steps of making the surface of a semiconductor substrate clean and flat in terms of atomic level by heating said semiconductor substrate in vacuum to a temperature at which reconstruction of the surface atoms of said semiconductor substrate takes place, then forming a structural buffer layer such as a native oxide layer and the like on said semiconductor substrate surface after the temperature of said semiconductor substrate was lowered to room temperature and finally subjecting the semiconductor substrate with said structural buffer layer formed on its surface to a thermal treatment performed in certain specified temperature and atmosphere. Accordingly, the semiconductor substrate surface becomes smooth in terms of atomic level and an ultra smooth semiconductor interface is formed.


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