Method and apparatus for detecting timing errors in digital circuit

Abstract

Disclosed is a system and method for simulating and detecting timing errors in digital circuit designs. The system consists of a logic simulator connected to various storage registers, a sequencer, and a randomizer, for simulating component functionality within the digital circuit design at sequential time increments using stored parametric data. The method includes selecting, for each component in a digital circuit design, a specific timing constraint from a range of possible timing constraint values, using a psuedo-random selection algorithm. The digital circuit is then simulated through a number of periods using this timing constraint. When an adequate number of periods have been simulated, a new set of timing constraints are selected. Timing requirement violations are detected and reported to a user.