The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 1995
Filed:
Mar. 31, 1993
Gary Brady, Portland, OR (US);
David Ellis, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Each of the remote high speed circuits of a digital system is provided with a sync pulse generation circuit for generating periodic sync pulses with a predetermined periodicity using a control value. Additionally, each of the remote high speed circuits is further provided with a sampling circuit for sampling the sync pulse generation control value, a comparison circuit for determining whether each of the sampled sync pulse generation control values are consistent, and an adjustment circuit for adjusting the sync pulse generation control value of the particular remote high speed circuit. Furthermore, a sync pulse generation coordinator comprising a clock selection circuit, a delay line, a delayed clock selection circuit, and a coordination pulse generation circuit is provided to the digital system for generating periodic coordination pulses. The periodic coordination pulses are used to control the sampling and comparison. A different delayed reference clock is used to generate the coordination pulses to control the sampling and comparison until a delayed reference clock that leads to consistent samples of control values for all remote high speed circuits is found. Once consistent sampling results are achieved, the sync pulse generation control values of the remote high speed circuits are adjusted accordingly using the adjustment circuits. The process is repeated until all sampled results are consistent and synchronized. The sampling is then continued to monitor for loss of synchronization.