The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 1995

Filed:

Mar. 21, 1994
Applicant:
Inventors:

Nobuaki Ohtsuka, Kawasaki, JP;

Junichi Miyamoto, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365218 ; 36523003 ; 36518911 ;
Abstract

Word lines are divided into a plurality of blocks in a row direction, and divided into a plurality of sections having e.g., four word lines in a column direction. An area where each block and each section are crossed is used as a sector. One sector includes four word lines. A control gate of a plurality of transistors constituting a memory cell is connected to each of the word lines, each drain is connected to each of the bit lines, and each source is connected to each of source lines in common. A source main decoder is provided in each section, source sub-decoders are provided in each sector. Each source sub-decoder includes each of supply circuits. The source main decoder outputs a sector selection signal in accordance with a row address signal, and a block decoder outputs block selection signals in accordance with a column address signal. One supply circuit is selected by the sector selection signal and the block selection signals, and the selected supply circuit supplies the sector selection signal outputted from the source main decoder source lines as an erase signal.


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