The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 1995
Filed:
Aug. 13, 1993
Cyrus Y Tsui, Los Altos, CA (US);
Albert L Chan, Palo Alto, CA (US);
Kapil Shankar, Fremont, CA (US);
Ju Shen, Saratoga, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
A structure and a method to implement in-system programming (ISP) and boundary-scan testing in an integrated circuit using the same pins to control both functions. The SDI, SCLK, MODE and SDO connections required for in-system programming and the TDI, TCK, TMS and TDO connections required for boundary-scan testing are multiplexed such that they are provided from the same four pins. An in-system programming enable pin is used to control the multiplexing of these pins. In an alternative embodiment, both in-system programming and boundary-scan testing are performed using the same pins and the same state machine. The test logic architecture specified in IEEE Standard 1149.1-1990 is utilized. To implement the in-system programming instructions, the instruction register of Std. 1149.1-1990 is modified to include private instructions which perform the desired programming functions.