Multiprocessor programmable interrupt controller system adapted to

Abstract

A multiprocessor programmable interrupt controller system, for use in a multiprocessor system in which one processor unit is a functional redundant checking (FRC) unit, has a synchronous interrupt bus, distinct from the system (memory) bus, with an interrupt bus clock that has a frequency that is a subharmonic of the FRC unit master CPU clock, for handling interrupt request (IRQ) related messages and maintaining synchronism between the master and checker CPUs of the FRC unit. Additional embodiments provide for the use of D-type flip-flop synchronizers to accommodate FRC units whose internal (core) clock or external bus clock are not harmonically related to the interrupt clock frequency. Each processor unit has an interrupt acceptance unit (IAU) coupled to the interrupt bus for the acceptance of IRQs and for broadcasting of IRQs generated by its associated on-chip processor. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two data wires for 2-bit parallel-serial data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to the lowest priority mode arbitration procedure also provides for uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done by means of the system bus.