The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 1995

Filed:

Feb. 08, 1994
Applicant:
Inventors:

Cheng-Yun Sun, Taichung, TW;

Yung-Jung Jan, Taipei Hsien, TW;

Ching-Hsiang Yang, Chia-Li, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365194 ; 365 78 ; 36518902 ; 36518912 ; 365240 ;
Abstract

The present invention discloses an apparatus for receiving an ordered sequence of input data and for delaying the output of a delay output item by a variable-length delay-time. The apparatus includes an input port for receiving the ordered sequence of input data and the variable-length delay-time. The apparatus further includes an integrated data storage, a random access memory (RAM) for storing the ordered sequence of input data according to a storage-order corresponding to the ordered sequence of the input data. The apparatus further includes a delay output port for accessing and outputting the delay output item in the storage means according to the variable-length delay-time and the storage-order such that the delay output item is delayed by the variable-length delay-time.


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Sun, Cheng-Yun. (1995). Variable length delay circuit utilizing an integrated memory device with (U.S. Patent No. 5406518). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5406518

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