The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 1995
Filed:
Dec. 21, 1993
Applicant:
Inventor:
Michael A Ang, Santa Clara, CA (US);
Assignee:
Vertex Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 68 ; 326 98 ;
Abstract
A GTL signal to CMOS level signal converter has a sense amplifier to receive the GTL signal and a clock signal and generate a first signal in response thereto. A buffer has a plurality of clocked stages for receiving the clock signal and the first signal and for generating the CMOS signal. A clock generates the clock and supplies the clock signal to the sense amplifier and the buffer.
Quick Actions:
Ang, Michael. (1995). Gtl to cmos level signal converter, method and apparatus (U.S. Patent No. 5406143). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5406143
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile