The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 1995

Filed:

Mar. 29, 1994
Applicant:
Inventors:

James R Pfiester, Austin, TX (US);

James D Hayden, Austin, TX (US);

Michael P Woo, Austin, TX (US);

Assignee:

Motorola Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437200 ; 437 41 ; 437195 ; 437203 ; 437228 ; 448D / ; 448D / ;
Abstract

A metal silicide interconnect (48, 92, 124) is formed in an integrated circuit using a sacrificial layer (30, 78, 108). In one embodiment a sacrificial layer of titanium nitride (30) is formed overlying a semiconductor substrate (12) and a polysilicon conductive member (20). The sacrificial titanium nitride layer (30) is then patterned and an underlying portion (40) of the semiconductor substrate (12), and a sidewall portion (42) of the polysilicon conductive member (20) are subsequently exposed. A metal layer (46) is deposited and then reacted with the exposed portion 40 of the semiconductor substrate (12) and the exposed sidewall (42) of the polysilicon conductive member (20) to form a metal silicide interconnect (48). The remaining portion of the sacrificial titanium nitride layer (38) is then removed after the metal silicide interconnect (48) has been formed without substantially altering the metal silicide interconnect (48).


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