Semiconductor memory having test circuit and test method thereof

Abstract

A semiconductor memory includes a plurality of memory cells which are arranged in a matrix and respectively store data, a plurality of bit lines and a plurality of word lines, connected to the plurality of memory cells, for performing read/write access of data to the memory cells, and a test circuit. In the test circuit, an external terminal sends test data and expected value data written in the memory cells. A simultaneous write circuit simultaneously writes the test data from the external terminal in the plurality of memory cells connected to a selected word line. A simultaneous comparison circuit simultaneously compares the test data written in the plurality of memory cells connected to the selected word line with the expected value data supplied from the external terminal in correspondence with the selected word line.