The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 1995

Filed:

Feb. 19, 1993
Applicant:
Inventors:

Mamoru Furuta, Hirakata, JP;

Tetsuya Kawamura, Hirakata, JP;

Tatsuo Yoshioka, Hirakata, JP;

Hiroshi Sano, Hirakata, JP;

Yutaka Miyata, Ikoma, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 40 ; 437 21 ; 437 29 ; 437913 ; 148D / ;
Abstract

In a method of manufacturing a thin film transistor, when impurity ions are introduced in a channel region between source and drain regions in a semiconductor layer, an insulator layer is first formed on the semiconductor layer. Then, impurity ions generated on high frequency discharge are introduced through the insulator layer into the semiconductor layer under a specified acceleration voltage. Then, the introduction depth of impurities and the amount of the impurities to be introduced in the channel region can be controlled or the threshold voltage of the thin film transistor can be controlled. This method can be applied to a large substrate.


Find Patent Forward Citations

Furuta, Mamoru. (1995). Method of manufacturing thin film transistor (U.S. Patent No. 5397718). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5397718

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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