Method of manufacturing low leakage and long retention time dram

Abstract

A method for making a DRAM MOSFET integrated circuit and resulting device having low leakage and long retention time in a semiconductor wafer is described. A pattern of gate dielectric and gate electrode structures is provided over the semiconductor wafer having a first conductivity imparting dopant in the cell array region and the peripheral circuits region of the integrated circuit. The pattern of gate dielectric and gate electrode structures as a mask for ion implantation to form lightly doped regions of a second and opposite conductivity imparting dopant in the semiconductor wafer wherein certain of the lightly doped regions within the cell array region are to be bit line regions and capacitor node regions. A capacitor is formed within the cell array region. An interlevel dielectric insulating layer is formed over the surface of the structure. A highly doped bit line contact is formed to the bit line regions. The structure is heated to anneal out the ion implantation damage in the lightly doped regions caused by the ion implantation into the lightly doped regions and to cause outdiffusion from the doped bit line contact layer to form a highly doped bit line contact within certain of the lightly doped regions wherein the low leakage and long retention time are the resulting circuit characteristics.