The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 1995
Filed:
Aug. 06, 1993
Applicant:
Inventors:
Katsuhiko Miki, Nishigou, JP;
Yukio Naruke, Choushi, JP;
Assignee:
Shin-Etsu Handotai Co., Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 10 ; 148D / ; 148D / ; 437 12 ; 437 19 ; 437 81 ; 437939 ; 437946 ; 437976 ; 437977 ;
Abstract
A method of controlling a misfit dislocation in a process of producing an epitaxial semiconductor wafer comprising a semiconductor substrate and an epitaxial layer deposited on the semiconductor substrate, an impurity concentration of the epitaxial layer differing from that of the semiconductor substrate, has the step of controlling the amount of an extrinsic strain caused on the back surface of the semiconductor substrate prior to the step of depositing the epitaxial layer, thereby controlling an occurrence of misfit dislocation caused in and near the interface between the semiconductor substrate and the epitaxial layer.