The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 1995
Filed:
Mar. 01, 1994
Sundaravarathan R Iyengar, San Jose, CA (US);
James Nadir, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A processor communicates over a memory bus with a main memory and a cache by asserting an address strobe signal (ADS) to initiate a memory access. The cache includes a cache controller and a tag random access memory (tag RAM). Internal cycles are tracked by a first logic in the tag RAM that responds to an external cycle (EXCYC) signal and asserts an internal cycle (INCYC) signal during a time when a request to the tag RAM is pending. A second logic combines the INCYC signal with the. ADS to generate an address strobe wait (ADSWAIT) signal. A third logic combines the ADSWAIT signal with the ADS to generate an address strobe cycle (ADSCYC) signal. A fourth logic responsive to one of several end-of-cycle signals generates a terminate signal to signify an end of a current cycle. A fifth logic asserts the EXCYC signal in response to the ADSCYC signal and unasserts the EXCYC signal in response to the terminate signal.