The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 1995
Filed:
Jun. 28, 1993
Gregory E Atwood, San Jose, CA (US);
Owen W Jungroth, Sonora, CA (US);
Neal R Mielke, Los Altos Hills, CA (US);
Branislav Vajdic, Los Gatos, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A reference scheme for verifying the erasing and programming in an electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate which employs a plurality of memory cells, each of which contains a floating gate. The reference scheme employs trimmable single cell reference devices for both the erase verify and program verify operations. The threshold voltages of the reference cells are trimmed to a level below (in the case of the erase verify reference cell) or above (in the case of the program verify reference cell) which all memory cells in the array will be considered in a particular program state (i.e., erased or programmed). In the case of the read reference device, a double-cell read referencing device combining the erase and program verify reference cells is described. Although, the double-cell referencing device is preferred, a trimmable read reference device is also taught.