Sram memory structure and manufacturing method thereof

Abstract

The invention provides an SRAM memory cell structure permitting increase of integration density while maintaining operation stability. A memory cell in the SRAM includes a pair of access transistors, a pair of driver transistors, and a pair of load transistors. The gate insulating film of access transistor is formed of a single layer of silicon oxide film, while the gate insulating film of driver transistor is formed of a stacked layer formed of a silicon oxide film and a silicon nitride film. The pair of load transistors are formed of two layers of polycrystalline silicon layers stacked upon each other with an insulating film therebetween. A source region and a drain region are formed in each of polycrystalline silicon layers with each channel region therebetween. One drain region forms a gate opposite to the other channel region, while the other drain region forms a gate opposite to the one channel region.