Multiple bit loaded line phase shifter

Abstract

A loaded line phase shifter includes a semiconductor substrate; a main transmission line one-quarter wavelength long disposed on the semiconductor substrate; loaded lines connected to opposite ends of the main line; first and second FETs with drain electrodes connected to the other ends of the loaded lines and grounded source electrodes; and a resonant circuit including a third FET and an inductor connected between the drain electrodes of said first and second FETs. A desired phase shift quantity of the phase shifter is determined by the characteristic impedance of the main line, the reactance components of the loaded lines, and the off-capacitances of the FETs. When the resonant circuit is closed in this structure, the susceptance of the loaded lines and the first and second FETs is equal to zero, resulting in a phase shift quantity equivalent to half of the phase shift quantity obtained when the resonant circuit is opened. Therefore, two different phase shift quantities are achieved in one phase shifter, resulting in a small-sized multiple-bit phase shifter.