Cmos tristateable buffer

Abstract

A CMOS buffer for a mixed or singular voltage system includes an input stage circuit for converting input data compatible with transistor-transistor logic (TTL) levels to an internal signal compatible with CMOS logic levels. The buffer also includes an output driver circuit generating a pair of drive signals and a first pair of control signals in response to the internal signal. The output driver predriver circuitry also receives as inputs an enable signal for controlling the tristateablity of the buffer, and a mode signal for selecting between relatively fast versus slow output switching. A final stage circuit is configured to provide relatively fast switching at the output node when the mode signal is high, and relatively slow switching at the output node when the mode signal is low. A feedback circuit couples the input data signal to the output node as well as receiving the pair of drive signals from the output predriver circuit. The feedback circuit generates the second pair of control signals coupled to the final stage circuitry which prevents leakage current from flowing within the buffer whenever the buffer is in a tristate mode of operation and a relatively high voltage is applied to the output node.