The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 1994

Filed:

Dec. 10, 1993
Applicant:
Inventors:

Robert B Richart, Austin, TX (US);

Shyam G Garg, Austin, TX (US);

Fei Wang, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 48 ; 437 43 ; 437 52 ; 437923 ;
Abstract

A flash EPROM device is provided for programmably storing digital data within a core array of electrically programmable transistors. A row or column within the array can be substituted for a spare or redundant row or column selectively connected to row or column decoder circuits by a redundancy select transistor. Self-aligned source regions within the array and redundancy select area are provided using a single mask for opening the self-aligned source regions and for implanting a light dosage of phosphorus directly into the underlying silicon substrate. Careful control and elimination of residue within the etched area via a subsequent wet etch helps ensure the implant edges are anisotropically controlled and isolated for subsequent lateral diffusion/drive-in. Accordingly, the flash EPROM device of a plurality of transistors within the array and within the redundancy select area are process controlled and demonstrate a significant reduction in threshold skewing. A result being an array of electrically programmable transistors which read, write and erase at substantially the same threshold level for each transistor.


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