The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 1994

Filed:

Oct. 11, 1991
Applicant:
Inventors:

Takashi Maruyama, Yokohama, JP;

Keiichi Kurakazu, Tachikawa, JP;

Susumu Kaneko, Kodaira, JP;

Hiroyuki Kida, Hitachi, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395325 ; 364D / ; 3642328 ; 3642412 ; 36424292 ; 3642653 ; 3642808 ;
Abstract

A bus error ascribable to a bus master module other than a central processing unit (CPU) is set as a specified factor for an exception process. When the exception process is requested, the CPU carries a corresponding service program for the exception process into execution without executing a process for altering and setting mask bits as is executed for an interrupt request. Thus, the exception process request specific to the bus error is not undesirably refused by the interrupt request etc. accepted before the bus error, and besides, a period of time which is expended before the start of the run of a service program corresponding to the bus error is shortened, with the result that the reliability of the process for the bus error attributed to the predetermined bus master module other than the CPU is enhanced.


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