Phase window test circuit

Abstract

The present invention provides a method and an apparatus for controlling and measuring the phase window of a data separator that is suitable for implementation in an automatic test equipment (ATE) system. The test circuit comprising cross-coupled flip-flops uses the pump up (PU) and pump down (PD) signals produced by a phase detector of a phase-locked loop (PLL) to digitally monitor the phase window. The PLL captures a fixed frequency data pattern provided to the data separator and tracks its frequency. The clock inputs of the cross-coupled flip-flops are driven by the pump up and pump down signals output by the phase detector. Once the PLL has captured the fixed frequency data pattern and settled, a single data bit is shifted from its initial position in the center of the phase window. The single data bit is shifted so that its phase leads or lags its initial position. When the single data bit is shifted in the data pattern, the phase detector correspondingly sets PU high, PD high, or both PU and PD high. By shifting the data bit so that its phase is first leading and then lagging, or vice versa, until the flip-flops change state, the edges of the phase window are determined. Due to the digital nature of this test circuit, the phase window of a data separator can be accurately measured by an ATE system.