The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 1994
Filed:
Mar. 15, 1993
James R Pfiester, Austin, TX (US);
James D Hayden, Austin, TX (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
A semiconductor memory cell (10) having a symmetrical layout is fabricated in first and second active regions (44, 46) of a semiconductor substrate (11). A first driver transistor (16) resides in the second active region (46), and a second driver transistor (20) resides in the first active region (44). The second driver transistor (20) has a gate electrode (55) overlying a portion of the first active region (44) and is electrically coupled to the second active region (46). A thin-film load transistor (18) resides over the first active region (44), the thin-film load transistor (18) has a thin-film channel layer (23) that overlies, and is aligned with, the gate electrode (55) of the second driver transistor (20). A second portion of the thin-film channel layer (23) extends away from the first active region (44) to form a Vcc node (36). A Vcc interconnect layer (82) overlies the thin-film load transistors and the driver transistors. The Vcc interconnect layer (82) is electrically isolated from the thin-film gate electrode and electrically contacts the second portion of the thin-film channel layer (23) at Vcc node (36). A thin-film load transistor (22) having structure corresponding with thin-film load transistor (20) resides over the second active region (46).