The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 1994
Filed:
Oct. 15, 1992
Applicant:
Inventor:
Hironobu Nakao, Kyoto, JP;
Assignee:
Rohm Co., Ltd., Kyoto, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 41 ; 437 44 ; 437 48 ; 437 52 ; 437228 ; 437229 ; 437984 ; 148D / ;
Abstract
When a semiconductor is manufactured by a resist mask process while using photolithography techniques, the gate wiring width is increased without increasing the cell area by providing a sidewall on the gate mask and using the sidewall as a mask. The sidewall is produced by applying a CVD oxide film to the mask and removing the oxide film by anisotropic etching. This provides a minimum gate line width of 0.7.mu. and a minimum space width of 0.3.mu..
Nakao, Hironobu. (1994). Method of manufacturing semiconductor device employing oxide sidewalls (U.S. Patent No. 5366913). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5366913
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile