The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 1994
Filed:
Oct. 16, 1992
Robert J Wojnarowski, Ballston Lake, NY (US);
Constantine A Neugebauer, Schenectady, NY (US);
Wolfgang Daum, Schenectady, NY (US);
Bernard Gorowitz, Clifton Park, NY (US);
Eric J Wildi, Niskayuna, NY (US);
Michael Gdula, Knox, NY (US);
Stanton E Weaver, Jr, Northville, NY (US);
Anthony A Immorlica, Jr, Manlius, NY (US);
Martin Marietta Corporation, Philadelphia, PA (US);
Abstract
In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.