The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 1994

Filed:

Jun. 04, 1993
Applicant:
Inventors:

Young I Kwon, San Jose, CA (US);

Louis H Liang, Los Altos, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
361813 ; 174 521 ; 257666 ; 257676 ; 361807 ;
Abstract

A package design configuration for an integrated-circuit die includes a leadframe having its bonding fingers connected to the periphery of an electrically-insulated, heat-conductive substrate, formed, for example, of a ceramic material. A number of electrically conductive traces, or bonding islands, serve as intermediate bonding locations for shorter bonding wires connecting bonding pads on the integrated-circuit die to the bonding fingers of the leadframe. The conductive traces serving as bonding islands are formed by deposition of thin-film material using semiconductor fabrication techniques or by deposition of thick-film material using printing techniques. Various shapes and configurations of the conductive traces are available, such as elongated rectangular patterns, or zigzag patterns. Alternatively, the electrically-insulated, heat-conductive ceramic substrate is attached to the die-attach pad of a conventional leadframe.


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