The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 1994

Filed:

Oct. 29, 1993
Applicant:
Inventors:

John M Angiulli, Lagrangeville, NY (US);

Arun K Ghose, Behala, IN;

Richard R Konian, Poughkeepsie, NY (US);

Samuel R Levine, Poughkeepsie, NY (US);

David Meltzer, Wappingers Falls, NY (US);

Wen-Yuan Wang, Hopewell Junction, NY (US);

Leon L Wu, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B / ; H03K / ;
U.S. Cl.
CPC ...
331 57 ; 331135 ; 3311 / ; 331179 ;
Abstract

A variable frequency digital ring oscillator which can be formed in a small area for use in testing of chips employs a ring oscillator formed of CMOS inverters, transmission gates and capacitors and CMOS logic as a voltage controlled ring oscillator. A wide range of frequency of oscillation is achieved with small number of components. The ring oscillator circuit's oscillator frequency is controlled only by DC voltages, such as may be provided by (but not limited to) a manufacturing chip tester. The output signal of the oscillator swings between Vdd and Vss and does not need additional level translation circuits to drive CMOS logic. The ring oscillator can be composed of an odd number of CMOS inverters connected in cascade to form a loop. We provide a CMOS transmission gate with PMOS and NMOS transistor device inserted between each adjacent inverter and a MOS capacitor connected between the output of each transmission gate and the Vss supply of the ring oscillator circuit (conventionally ground). The gate voltages of the PMOS and NMOS transistors in the transmission gate are different and provide a different DC voltage between Vdd and Vss. Variation of the gate voltages of the transmission gates controls the frequency of oscillation of the circuit. The use of a plurality of cascaded delay elements between inverters achieves a wider range of oscillation frequency than possible with a single delay element.


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