The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 1994

Filed:

Jun. 24, 1993
Applicant:
Inventors:

John M Boyd, Woodlawn, CA;

Joseph P Ellul, Nepean, CA;

Sing P Tay, Nepean, CA;

Assignee:

Northern Telecom Limited, Montreal, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 67 ; 437 62 ; 437228 ; 148D / ;
Abstract

A method is provided for forming a fully planarized trench isolated region in a semiconductor substrate for an integrated circuit, for example, a trench isolated field oxide region, or a trench isolated semiconductor region in which thin film semiconductor devices are formed. Planarization is accomplished by a chemical mechanical polishing process in which coplanar layers of a chemical mechanical polish resistant material are provided in a centre region of wide trenches as well as on the semiconductor substrate surface adjacent the trenches. The chemical mechanical polish resistant layer in the centre region of a wide trench forms an etch stop to prevent dishing of layers filling the trench during overall wafer planarization by chemical mechanical polishing. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuit structures.


Find Patent Forward Citations

Loading…