Serial access memory

Abstract

A serial access memory includes a pair of bit lines, a plurality of memory cells each coupled to one of the bit lines and a pair of data lines. The serial access memory also includes a sense amplifier drive line, a sense amplifier, data latch circuit, data transfer circuit and a drive capability control circuit. The sense amplifier drive line is coupled to a potential source for supplying a sense amplifier drive signal from the potential source. The sense amplifier is coupled to the bit lines and the sense amplifier drive line for amplifying a difference of electrical potentials appeared on the bit lines in response to the sense amplifier drive signal. The data latch circuit is coupled to the bit lines and the data lines for latching the amplified electrical potentials appeared on the bit lines as data. The data transfer circuit is coupled between the bit lines and the data latch circuit for controlling an electrical connection between the bit lines and the data latch circuit. The drive capability control circuit is coupled between the power potential source and the sense amplifier drive line for controlling an electrical connection between them. The drive capability control circuit controls its drive capability so as to control a sense amplification capability of the sense amplifier.