Semiconductor memory device having an energy gap for high speed operation

Abstract

A semiconductor device is provided comprising a nonvolatile memory cell through which an LSI and a higher operating speed are achieved. A drain region, an insulating layer partly overlaying the drain region, and a gate electrode formed on the insulating layer are formed on a semiconductor substrate thereby making up a memory cell without a source region. An energy gap between the conduction and valence bands of a semiconductor section including the drain region and the semiconductor substrate is preset to a value corresponding to a first set voltage difference between the drain and the gate. The energy gap between the valence bands (or the conduction bands) of the insulating layer and the semiconductor section at the interface between the semiconductor section and the insulating layer is preset to a value corresponding to a second set voltage difference between the drain and the substrate. Write operations are done by trapping in the insulating layer a charge which has jumped the valence band of the insulating layer at a voltage not less than the second set voltage difference. Read operations are done at a voltage not less than the first set voltage but not more than the second set voltage. Erase operations are done by releasing a charge trapped or by implanting a reverse charge.