The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 1994
Filed:
Dec. 19, 1991
Greg A Peek, Beaverton, OR (US);
Craig D Cedros, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A circuit and processing logic is used to test, configure, and control the operation of computer system resource addressing control signals. The programmable circuit of the present invention determines when, in an I/O access cycle, the resource addressing control (IOCHRDY) signal should be activated by an I/O mapped system resource. The present invention includes lost circuitry for determining whether a particular system resource operates best in a late IOCHRDY mode or an early IOCHRDY mode. The test logic will force the IOCHRDY signal to remain active for an extended period of time. By extending the deactivation time of the IOCHRDY signal far beyond the time at which the deactivation would normally occur, the responsiveness of a command strobe (IORD/IOWR) may be tested. If the deactivation of the command strobe IORD/IOWR follows the extended deactivation time of the IOCHRDY signal, the command strobe (IORD/IOWR) is properly responsive to the IOCHRDY signal and proper operation of the I/O access control logic is verified. If, however, the extended activation of the IOCHRDY signal causes the command strobe (IORD/IOWR) to deactivate prior to the deactivation of the IOCHRDY signal, a nonresponsive command strobe (IORD/IOWR) signal is present and thus a failure condition is detected. A processor-readable bit in a control register indicates a successful or unsuccessful IOCHRDY test condition.