The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 1994
Filed:
Aug. 31, 1992
Andrew J Read, Sunnyvale, CA (US);
Mark S Papamarcos, San Jose, CA (US);
Wayne P Heideman, San Jose, CA (US);
Robert K Mardjuki, Peasanton, CA (US);
Robert K Couch, Santa Cruz, CA (US);
Peter R Jaeger, San Jose, CA (US);
William F Kappauf, San Jose, CA (US);
Lawrence C Widdoes, Jr, Los Altos Hills, CA (US);
Louis K Scheffer, Los Altos Hills, CA (US);
Synopsys Inc., Mountain View, CA (US);
Abstract
An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimulus pattern sequences, pin electronics circuitry which is used for driving the pattern sequences on the pattern bus to the hardware modeling element and then sensing the five state values of the hardware modeling element pins, and an adapter that is used for fixturing the hardware modeling element to the pin electronics circuitry with the adapter supporting live insertion into a powered hardware modeling system.