The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 1994
Filed:
Dec. 07, 1993
Gerold W Neudeck, West Lafayette, IN (US);
Suresh Venkatesan, West Lafayette, IN (US);
Purdue Research Foundation, West Lafayette, IN (US);
Abstract
A method for forming a dual-gated Semiconductor-On-Insulator (SOI) field effect transistor for integrated circuits includes the formation of a gate/oxide/channel/oxide/gate stack on top of an insulating layer. The process begins with the formation of a first gate electrode and first oxide layer on an insulating layer. Then, a seed hole in the insulating layer is formed exposing the underlying substrate. This is followed by the epitaxial lateral overgrowth (ELO) of monocrystalline silicon, for example, from the seed hole to on top of the first oxide layer. This monocrystalline layer forms the device channel. A second oxide and second gate electrode layer are then grown and deposited, respectively. Subsequent etch steps employing sidewall spacers are then employed to form a multilayered stack having self-aligned first and second gate electrodes. Sidewall seed holes are then used to epitaxially grow monocrystalline source and drain regions from the channel. In-situ doping can be provided to form a lightly doped source (LDS) and drain (LDD) structure with vertically displaced source and drain contacts.