The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 1994

Filed:

Dec. 30, 1993
Applicant:
Inventors:

Toshiaki Murao, Kawasaki, JP;

Takeo Kikuchi, Choufu, JP;

Toshihiko Iryu, Kawasaki, JP;

Hidenori Nomura, Kasugai, JP;

Hiroyuki Sugamoto, Nishikasugai, JP;

Assignees:

Fujitsu Limited, Kawasaki, JP;

Fujitsu VLSI Limited, Kasugai, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257208 ; 257210 ;
Abstract

A wafer-scale semiconductor integrated circuit device includes a wafer, a plurality of chips formed on the wafer, each of the chips having an internal logic circuit, interconnection lines mutually connecting the chips, and clamping circuits which are coupled to chips from among the chips which are located at a periphery of an arrangement of the chips and which prevent the interconnection lines related to the chips located at the periphery from being in a floating state.


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Murao, Toshiaki. (1994). Wafer-scale semiconductor integrated circuit device and method of (U.S. Patent No. 5349219). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5349219

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