Dram with memory cells having access transistor formed on solid phase

Abstract

Access transistors of memory cells in a DRAM are formed in a solid phrase epitaxial single crystalline layer on the surface of a silicon substrate. A bit line extending over the surface of an element isolation and insulation film is formed by patterning a polycrystalline silicon layer extending to the single crystalline silicon layer as a layer. A stacked capacitor is connected to one source/drain of the access transistor through a conductive layer extending to the single crystalline silicon layer and over a field oxide film. Part of the stacked capacitor extends over the bit line. The connection region of the bit line, the capacitor and the source/drain is formed above the element isolation and insulation film, so that the source/drain region of the access transistor can be reduced.