The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 1994
Filed:
Jul. 27, 1993
Harold Kohn, Endwell, NY (US);
Donald J Lazzarini, Vestal, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is a method for manufacturing a stacked circuitized flex structure. The structure is a laminate for Z-axis communication within a parallel processor. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Z-axis circuitization is carried out by providing vias and through holes in individual circuitized flex strips. These vias and through holes are circuited and plated. This is followed by filling the vias and through holes with solder and forming solder bumps at the tops and bottoms of the vias and through holes. A sticker sheet with clearance holes for the solder bumps is provided, and a plurality of the circuitized flex strips are laid up for lamination to form a stack of circuitized flexible strips. Lamination is carried out at elevated pressure and temperature to crush the solder bumps, bond, and homogenize solder bump material and fuse the sticker sheets. Next, the stack is cooled to solidify the homogenized solder bump material.