Packages for stacked integrated circuit chip cubes

Abstract

This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cuboid structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate and within which corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contain solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate surface or the pin-like structures can be adapted for insertion into apertures in a second substrate. The second substrate provides a means for electrically inter-connecting a plurality of these cuboids. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cuboid structures.