The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 1994
Filed:
Jun. 02, 1993
Yoshihiko Nagayasu, Kawasaki, JP;
Fuji Electric Co., Ltd., Kawasaki, JP;
Abstract
A low-concentration region is formed by ion implanting a P-well with P.sup.+ using a gate as a mask, then an N-well is ion-implanted with As.sup.+ and B.sup.+ using a resist film and the gate as a mask to form a DMOSFET having a double-diffused drain structure. Then, the gate and an insulation material are used as a mask to ion-implant the P-well with As.sup.+ to form a CMOSFET having a lightly doped drain structure. After that, the N-well is ion-implanted with BF.sub.2.sup.+ through an opening to connect a P base region with a P base-contact region. The source/drain and p-base regions of the DMOS device are formed deeper than those of the CMOS device. Incorporation of a bipolar transistor is also disclosed. All devices are formed on the same substrate.