Semiconductor device having a decoding circuit for selection chips

Abstract

There is disclosed a semiconductor device having a plurality of chips in which a predetermined extended addresses are allocated for each of the chips to select the chips in a multiple-chip module, the device comprising: a plurality of semiconductor chip selectors equipped in said semiconductor device, for supplying an internal chip select signals to select the chips in response to said extended addresses and a module select signal; and each of said semiconductor chip selectors having a plurality of decoders for receiving the extended addresses and outputting a predetermined logic signal, and an AND gate for receiving said module select signal and said logic signal of each of said decoders and outputting said internal chip select signals. Accordingly, in packaging semiconductor chips in accordance with the invention, a semiconductor chip module can be miniatured more, processing steps of such semiconductor chip module can be reduced, and input and output terminals of such semiconductor chip module can be reduces in the number so that the invention can improve access time or delay time in the module.