The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 1994

Filed:

Oct. 01, 1993
Applicant:
Inventor:

Paul C Tong, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 31 ; 437 59 ; 257370 ; 257565 ; 148D / ;
Abstract

A process for manufacturing an integrated circuit having both field effect and bipolar transistors provides, in one embodiment, a polycide film over the gate and field oxides. The polycide film is patterned such that a protective structure of gate material is formed on top the base region while the gate of the FET is formed, in a single process step. Ionic species are implanted to form the source and drain and the collector contact. The protective structure of gate material in the active region of the bipolar transistor is removed just before the base region is implanted to form the base. In a second embodiment, a silicon nitride oxidation mask for field oxide regions is formed over the bipolar transistor and the field effect transistor active regions. The portion of the nitride oxidation mask is removed only from the FET active regions after field oxide regions are formed. The portion of the nitride oxidation mask is left intact through formation of the gate regions of the FETs, formation of the oxide spacers of the FET active regions, and the formation of source and drain regions of the NMOS transistor. The nitride oxidation mask over the bipolar active region is removed prior to the base implant step. With the nitride oxidation mask over the bipolar transistor active region, a V.sub.T implant into the FET active region is performed.


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