The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 1994

Filed:

Dec. 31, 1992
Applicant:
Inventors:

Richard T Traskos, Brooklyn, CT (US);

John A Olenick, Brockport, NY (US);

Assignee:

Rogers Corporation, Rogers, CT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
29830 ; 29852 ; 156 89 ; 156902 ; 264 61 ;
Abstract

Methods of fabricating multilayer circuits are presented. In accordance with the present invention, a plurality of circuit layers are stacked, one on top of the other. At least one of the circuit layers comprise a substrate composed of a polymeric material capable of undergoing bonding such as a fluoropolymeric based substrate having vias therethrough and a circuit comprised of a layer of suitable conductive material. A fusible conductive bonding material (e.g., solder) or a noble metal is applied wherever electrical connections are desired. At least one other of the circuit layers comprises a cofired multilayer ceramic circuit having vias and circuits comprised of a layer of suitable conductive material with a fusible conductive bonding material (e.g., solder) or a noble metal applied wherever electrical connections are desired. Once stacked the circuits are subjected to lamination under heat and pressure to adhere each polymeric substrate to an adjacent ceramic substrate and to diffuse the noble metal or fuse the solder layers together to form an integral multilayer circuit having solid conductive interconnects.


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