The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 1994
Filed:
Dec. 10, 1992
Richard A Conti, Mount Kisco, NY (US);
Kenneth DeVries, Hopewell Junction, NY (US);
James F White, Newburgh, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A metal connection for an integrated circuit device is effectively 'cast' in place at any level of an integrated circuit. The 'mold' for the connection is formed by depositing and patterning a sacrificial material, such as aluminum oxide or other metal oxides, and covering the sacrificial material with a protective material such as silicon dioxide or other insulators. After forming bore holes to the deposit of sacrificial material through the protective layer, the sacrificial material is removed by isotropic etching to form a cavity beneath and at least partially overlaid by the protective layer. Alternatively, a defect may be produced below the protective layer and filled with metal either with or without enlargement by further removal of material. This cavity is then filled with metal by deposition of the metal by, for instance, evaporation, sputtering and chemical vapor deposition or combinations thereof. Connections formed by this technique can be produced at any level of the integrated circuit and do not interfere with surface wiring. A plurality of such connections may be simultaneously formed at the same or different levels of the integrated circuit and the method may be repeated to form multi-level wiring patterns.