The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 1994
Filed:
Dec. 24, 1992
Steven K Sullivan, Beaverton, OR (US);
Joseph R Peter, Beaverton, OR (US);
Tektronix, Inc., Wilsonville, OR (US);
Abstract
A CMOS-compatible peak detection circuit includes a differential amplifier stage (10), an active peak holding circuit (12), and a passive peak holding circuit (14). The differential amplifier stage (10) produces an amplifier output signal that is responsive to the difference between an input signal being monitored and feedback from the active peak holding circuit (12). Both the active peak holding circuit (12) and the passive peak holding circuit (14) store a charge representing a voltage level that is indicative of the peak amplitude of the amplifier output signal during a time interval, the time interval occurring while a disable signal is inactive. The active peak holding circuit (12) provides the maximum value signal as feedback to the differential amplifier stage (10). The passive peak holding circuit (14) provides a max signal output corresponding to the maximum value to a voltage follower stage (16) that makes it available as an output when a readback enable signal goes active. The active and passive peak holding circuits (12,14) are disconnected from the output of the differential amplifier stage (10) when a disable signal is active. A reset signal discharges capacitor storage (C1,C2) in the peak holding circuits (12,14) when it goes active. The readback enable and reset signals only go active during the time that the disable signal is active. To conserve power, a bias generation circuit (18) provides bias signals to the differential amplifier stage (10) enabling it to conduct only when the disable signal is inactive.