Cmos-based peak detector for fast-in, slow-out min/max detection

Abstract

A fast, CMOS-based peak detection cell circuit and related methods can be used to determine maximum and minimum excursions of a signal being monitored during the very short intervals between high speed sampling points. Two nodes, 'a' and 'b', of such a circuit are precharged. Node 'a' is then connected to the signal to be monitored. A PMOS transistor, with node 'a' on its gate and node 'b' on its drain, then causes a capacitance at node 'b' to discharge to the voltage level of node 'a' plus a constant offset voltage. Node 'b' thus tracks downward excursions of the signal to be monitored, but not upward ones. Therefore, the voltage level at node 'b' at the end of the acquisition interval is a function of the lowest voltage level assumed by the signal. A trio of such minimum detection cell circuits can be used together to find minimum and maximum behaviors of a differential complementary pair of signals. One cell is used to find the minimum of the signal, another the minimum of its complement, and the third the minimum of a common mode signal associated with the signal and its complement. Appropriate subtraction then produces actual signal minimums and maximums. An alternative embodiment for use with longer hold windows has a third node, 'c', that is isolated from sub-threshold currents that would otherwise corrupt the analog data over time.