Carrier injection dynamic random access memory having stacked depletion

Abstract

A carrier injected dynamic random access memory is defined. A depletion region adjacent to a source/drain region of a transistor is used as a storage cell in a memory array, and logic levels may then be measured by sensing the conductive portion. A low logic level is stored by a reduced formation of the depletion adjacent the conductive portion. These logic levels are sensed and periodically refreshed by conduction through the access device. The logic levels may be read by measuring potential through the access device, or by measuring punch through voltage between the source/drain region and a nearby conductive region. As the level of injected carriers increases, the punch through also increases. A punch through results in a readable increase in current through the access device, thereby providing an indicia of a in logic level.