The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 1994

Filed:

Jul. 23, 1992
Applicant:
Inventors:

Kazuhiro Sakashita, Hyogo, JP;

Terukazu Yusa, Hyogo, JP;

Isao Takimoto, Hyogo, JP;

Takeshi Hashizume, Hyogo, JP;

Tatsunori Komoike, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
3074821 ; 3074651 ; 3073031 ; 257207 ;
Abstract

In designing a layout of a semiconductor integrated circuit device having a large scale circuit block and logic circuit elements provided together, a power supply connecting line is formed rectilinearly to increase the integration density, reduce power supply noise and achieve automation of layout and interconnection. The semiconductor integrated circuit device includes one large scale circuit block and a plurality of logic circuit elements. VDD and GND annular power supply interconnecting lines are provided to surround the large scale circuit block. The annular power supply interconnecting lines extending in the lateral direction are divided into two lines to be disposed, respectively. Connection of the logic circuit elements and the annular power supply interconnecting lines are made by rectilinear VDD and GND power supply branch interconnecting lines.


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