The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 1994

Filed:

Sep. 08, 1993
Applicant:
Inventor:

Masahiko Yanagi, Tenri, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
365 52 ; 437189 ; 437190 ; 437228 ; 427534 ;
Abstract

A semiconductor memory device including a substrate on which a memory cell array portion and a peripheral circuit portion for the memory cell array portion are provided, the surface of the memory cell array portion being higher than the surface of the peripheral circuit portion. A glass layer is formed on the peripheral circuit portion with the glass layer having a predetermined thickness for offsetting the difference in height between the surface of the memory cell array portion and that of the peripheral circuit portion, so as to provide a substantially even surface over the memory cell array portion and the peripheral circuit portion. A metal wiring for the memory cell array portion and the peripheral circuit portion is formed in a predetermined pattern on the substantially even surface.


Find Patent Forward Citations

Yanagi, Masahiko. (1994). Semiconductor memory device (U.S. Patent No. 5313417). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5313417

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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