The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 1994
Filed:
Sep. 25, 1992
Daniel R Brasen, San Jose, CA (US);
James D Shiffer, II, Fremont, CA (US);
Mark R Hartoog, Los Gatos, CA (US);
Sunil Asktaputre, San Jose, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
Flexible routing of gate arrays increases routing efficiency, provides for the routing of functional blocks with other gates in the gate array, and provides structures for flexible power routing, particularly of gate arrays having functional blocks. In particular, a gate-array-implemented integrated circuit is designed using a computer by representing in computer memory a gate array base, placing gate array cells on the gate array base in placement rows each having a uniform height and separated by routing channels in which no gate array cells are placed, and routing in the routing channel connections between placement rows according to a netlist, during routing increasing the size of a routing channel if required and decreasing the size of a routing channel if possible by changing the placement of at least one placement row by an amount less than half the height of the placement row. Routing channel size is therefore flexibly adjusted 'on-the-fly' during routing, increasing routing efficiency. The adjustment of routing channels in small (5 track) increments is made possible by defining 'tall' macros (four transistor rows high) made of 'small' (5 track high) transistors.