Isolation technique for silicon germanium devices

Abstract

The present invention is an isolation structure for use with FET or bipolar devices incorporating a silicon-germanium layer in which the semiconductor devices are isolated by trench structures. A trench is etched through a pad layer, a single crystal silicon layer, a silicon-germanium layer, and finally, into the silicon substrate. The silicon-germanium layer is interposed between the single crystal silicon layer and the silicon substrate and the pad layer covers the single crystal silicon layer. The trench sidewall exposes the silicon-germanium layer. A single crystal silicon layer is formed as a trench liner. This silicon trench liner is then oxidized to passivate the trench isolation. The trench can then be filled with a dielectric without the devices being affected by parasitic leakage caused by the silicon-germanium layer exposed by the trench isolation.